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19-3943; Rev 3; 4/09
27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers
General Description
The MAX9248/MAX9250 digital video serial-to-parallel converters deserialize a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel control data. The separate video and control phases take advantage of video timing to reduce the serial-data rate. The MAX9248/MAX9250 pair with the MAX9247 serializer to form a complete digital video transmission system. For operating frequencies less than 35MHz, the MAX9248/ MAX9250 can also pair with the MAX9217 serializer. The MAX9248 features spread-spectrum capability, allowing output data and clock to spread over a specified frequency range to reduce EMI. The data and clock outputs are programmable for a spectrum spread of 4% or 2%. The MAX9250 features output enable input control to allow data busing. Proprietary data decoding reduces EMI and provides DC balance. The DC balance allows AC-coupling, providing isolation between the transmitting and receiving ends of the interface. The MAX9248/MAX9250 feature a selectable rising or falling output latch edge. ESD tolerance is specified for ISO 10605 with 10kV Contact Discharge and 30kV Air-Gap Discharge. The MAX9248/MAX9250 operate from a +3.3V 10% core supply and feature a separate output supply for interfacing to 1.8V to 3.3V logic-level inputs. These devices are available in a 48-lead LQFP package and are specified from -40C to +85C or -40C to +105C.
Features
o Programmable 4% or 2% Spread-Spectrum Output for Reduced EMI (MAX9248) o Proprietary Data Decoding for DC Balance and Reduced EMI o Control Data Deserialized During Video Blanking o Five Control Data Inputs are Single-Bit-Error Tolerant o Output Transition Time is Scaled to Operating Frequency for Reduced EMI o Staggered Output Switching Reduces EMI o Output Enable Allows Busing of Outputs (MAX9250) o Clock Pulse Stretch on Lock o Wide 2% Reference Clock Tolerance o Synchronizes to MAX9247 Serializer Without External Control o ISO 10605 and IEC 61000-4-2 Level 4 ESD Protection o Separate Output Supply Allows Interface to 1.8V to 3.3V Logic o +3.3V Core Power Supply o Space-Saving LQFP Package o -40C to +85C and -40C to +105C Operating Temperature Ranges
MAX9248/MAX9250
Applications
Navigation System Displays In-Vehicle Entertainment Systems Video Cameras LCD Displays
PART MAX9248ECM+ MAX9248ECM/V+ MAX9248GCM+ MAX9248GCM/V+ MAX9250ECM+ MAX9250ECM/V+ MAX9250GCM+ MAX9250GCM/V+
Ordering Information
TEMP RANGE -40C to +85C -40C to +85C -40C to +105C -40C to +105C -40C to +85C -40C to +85C -40C to +105C -40C to +105C PIN-PACKAGE 48 LQFP 48 LQFP 48 LQFP 48 LQFP 48 LQFP 48 LQFP 48 LQFP 48 LQFP
+Denotes a lead(Pb)-free/RoHS-compliant package. /V denotes an automotive qualified part.
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers MAX9248/MAX9250
ABSOLUTE MAXIMUM RATINGS
VCC_ to _GND........................................................-0.5V to +4.0V Any Ground to Any Ground...................................-0.5V to +0.5V IN+, IN- to LVDSGND............................................-0.5V to +4.0V IN+, IN- Short Circuit to LVDSGND or VCCLVDS ........Continuous (R/F, OUTEN, RNG_, REFCLK, SS PWRDWN) to GND................................. -0.5V to (VCC + 0.5V) (RGB_OUT[17:0], CNTL_OUT[8:0], DE_OUT, PCLK_OUT, LOCK) to VCCOGND .............................-0.5V to (VCCO + 0.5V) Continuous Power Dissipation (TA = +70C) 48-Lead LQFP (derate 21.7mW/C above +70C).....1739mW ESD Protection Machine Model (RD = 0, CS = 200pF) All Pins to GND............................................................200V Human Body Model (RD = 1.5k, CS = 100pF) All Pins to GND..............................................................2kV ISO 10605 (RD = 2k, CS = 330pF) Contact Discharge (IN+, IN-) to GND ............................10kV Air-Gap Discharge (IN+, IN-) to GND ............................30kV IEC 61000-4-2 (RD = 330, CS = 150pF) Contact Discharge (IN+, IN-) to GND ............................10kV Air-Gap Discharge (IN+, IN-) to GND ............................15kV Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC_ = +3.0V to +3.6V, PWRDWN = high, differential input voltage VID = 0.05V to 1.2V, input common-mode voltage VCM = VID / 2 to VCC - VID / 2, TA = -40C to +105C, unless otherwise noted. Typical values are at VCC_ = +3.3V, VID = 0.2V, VCM = 1.2V, TA = +25C.) (Notes 1, 2)
PARAMETER High-Level Input Voltage Low-Level Input Voltage SYMBOL VIH VIL VIN = -0.3V to 0 (MAX9248/ MAX9250ECM), PWRDWN = V = -0.15V to 0 (MAX9248/ IN high or low MAX9250GCM), VIN = 0 to (VCC + 0.3V) Input Clamp Voltage VCL ICL = -18mA IOH = -100A High-Level Output Voltage VOH IOH = -2mA, RNG1 = high IOH = -2mA, RNG1 = low IOL = 100A Low-Level Output Voltage VOL IOL = 2mA, RNG1 = high IOL = 2mA, RNG1 = low High-Impedance Output Current Output Short-Circuit Current IOZ IOS PWRDWN = low or OUTEN = low, VO = -0.3V to (VCCO + 0.3V) RNG1 = high, VO = 0 RNG1 = low, VO = 0 -10 -10 -7 VCCO - 0.1 VCCO - 0.35 VCCO - 0.4 0.1 0.3 0.35 +10 -50 -40 A mA V V CONDITIONS MIN 2.0 -0.3 TYP MAX VCC + 0.3 +0.8 UNITS V V SINGLE-ENDED INPUTS (R/F, OUTEN, RNG0, RNG1, REFCLK, PWRDWN, SS)
Input Current
IIN
-100
+20
A
-20
+20 -1.5 V
SINGLE-ENDED OUTPUTS (RGB_OUT[17:0], CNTL_OUT[8:0], DE_OUT, PCLK_OUT, LOCK)
2
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27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC_ = +3.0V to +3.6V, PWRDWN = high, differential input voltage VID = 0.05V to 1.2V, input common-mode voltage VCM = VID / 2 to VCC - VID / 2, TA = -40C to +105C, unless otherwise noted. Typical values are at VCC_ = +3.3V, VID = 0.2V, VCM = 1.2V, TA = +25C.) (Notes 1, 2)
PARAMETER LVDS INPUT (IN+, IN-) Differential Input High Threshold Differential Input Low Threshold Input Current VTH VTL IIN+, IIN(Note 3) (Note 3) PWRDWN = high or low (Note 3) PWRDWN = MAX9248/MAX9250ECM high or low MAX9248/MAX9250GCM Input Bias Resistor (Note 3) RIB VCC_ = MAX9248/MAX9250ECM 0 or open, PWRDWN = 0 or open, MAX9248/MAX9250GCM Figure 1 VCC_ = 0 or open, PWRDWN = 0 or open (Note 3) 2.5MHz 5MHz 5MHz 10MHz 10MHz 20MHz 20MHz 42MHz 2.5MHz 5MHz 5MHz 10MHz 10MHz 20MHz 20MHz RNG1 = high RNG0 = high Power-Down Supply Current ICCZ (Note 4) 35MHz 42MHz -50 -40 42 42 42 60 60 60 +40 78 88 78 k 50 mV mV A SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX9248/MAX9250
42 -60
60
88 +60 A
Power-Off Input Current POWER SUPPLY
IINO+, IINO-
RNG1 = low RNG0 = low MAX9250 CL = 8pF, worst-case pattern, Figure 2 RNG1 = low RNG0 = high RNG1 = high RNG0 = low RNG1 = high RNG0 = high Worst-Case Supply Current RNG1 = low RNG0 = low MAX9248 CL = 8pF, worst-case pattern, Figure 2 RNG1 = low RNG0 = high RNG1 = high RNG0 = low
19 33 28 49 33 59 45 89 31 48 40 70 49 87 68 100 120 50 A mA
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3
27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers MAX9248/MAX9250
AC ELECTRICAL CHARACTERISTICS
(VCC_ = +3.0V to +3.6V, CL = 8pF, PWRDWN = high, differential input voltage VID = 0.1V to 1.2V, input common-mode voltage VCM = VID / 2 to VCC - VID / 2, TA = -40C to +105C, unless otherwise noted. Typical values are at VCC_ = +3.3V, VID = 0.2V, VCM = 1.2V, TA = +25C.) (Notes 3, 5)
PARAMETER REFCLK TIMING REQUIREMENTS Period Frequency Frequency Variation Duty Cycle Transition Time SWITCHING CHARACTERISTICS MAX9248/ MAX9250ECM RNG1 = high Output Rise Time tR Figure 3 RNG1 = low MAX9248/ MAX9250GCM MAX9248/ MAX9250ECM MAX9248/ MAX9250GCM MAX9248/ MAX9250ECM MAX9248/ MAX9250ECM RNG1 = low MAX9248/ MAX9250GCM 2.2 2.2 2.8 2.8 1.9 2.3 2.3 0.4 x tT 0.4 x tT 0.35 x tT 0.35 x tT 0.45 x tT 0.45 x tT 0.4 x tT 0.4 x tT 33,600 x tT 16,928 x tT fREFCLK fREFCLK + 3.6% + 4.0% fREFCLK fREFCLK - 4.4% - 4.0% fREFCLK fREFCLK + 1.8% + 2.0% fREFCLK fREFCLK - 2.2% - 2.0% fREFCLK + 4.4% fREFCLK - 3.6% fREFCLK + 2.2% fREFCLK - 1.8% MHz 4.6 4.9 ns 5.2 6.1 4.0 4.3 5.2 0.6 x tT 0.6 x tT ns ns ns ns ns ns tT fCLK fCLK DC tTRAN 20% to 80% MAX9248/MAX9250ECM MAX9248/MAX9250GCM MAX9248/MAX9250ECM MAX9248/MAX9250GCM REFCLK to serializer PCLK_IN 23.8 28.6 2.5 2.5 -2.0 40 50 400.0 400.0 42.0 35.0 +2.0 60 6 ns MHz % % ns SYMBOL CONDITIONS MIN TYP MAX UNITS
RNG1 = high Output Fall Time tR Figure 3
PCLK_OUT High Time PCLK_OUT Low Time Data Valid Before PCLK_OUT Data Valid After PCLK_OUT PLL Lock to REFCLK
tHIGH tLOW tDVB tDVA tPLLREF
Figure 4 Figure 4 Figure 5 Figure 5 MAX9248, Figure 8 MAX9250, Figure 7 SS = high, Figure 11 Maximum output frequency Minimum output frequency Maximum output frequency Minimum output frequency
Spread-Spectrum Output Frequency (MAX9248)
fPCLK_OUT SS = low, Figure 11
4
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27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC_ = +3.0V to +3.6V, CL = 8pF, PWRDWN = high, differential input voltage VID = 0.1V to 1.2V, input common-mode voltage VCM = VID / 2 to VCC - VID / 2, TA = -40C to +105C, unless otherwise noted. Typical values are at VCC_ = +3.3V, VID = 0.2V, VCM = 1.2V, TA = +25C.) (Notes 3, 5)
PARAMETER Spread-Spectrum Modulation Frequency Power-Down Delay SS Change Delay Output Enable Time Output Disable Time SYMBOL fSSM tPDD tSSPLL tOE tOZ Figure 11 Figures 7, 8 MAX9248, Figure 17 MAX9250, Figure 8 MAX9250, Figure 9 10 10 CONDITIONS MIN TYP fREFCLK / 1024 100 32,800 x tT 30 30 MAX UNITS kHz ns ns ns ns
MAX9248/MAX9250
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH and VTL. Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested at TA = +25C. Note 3: Parameters are guaranteed by design and characterization, and are not production tested. Limits are set at 6 sigma. Note 4: All LVTTL/LVCMOS inputs, except PWRDWN at 0.3V or VCC - 0.3V. PWRDWN is 0.3V, REFCLK is static. Note 5: CL includes probe and test jig capacitance.
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5
27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers MAX9248/MAX9250
Typical Operating Characteristics
(VCC_ = +3.3V, CL = 8pF, TA = +25C, unless otherwise noted.)
WORST-CASE PATTERN SUPPLY CURRENT vs. FREQUENCY
MAX9248/50 toc01
OUTPUT TRANSITION TIME vs. OUTPUT SUPPLY VOLTAGE (VCCO)
MAX9248/50 toc02
OUTPUT TRANSITION TIME vs. OUTPUT SUPPLY VOLTAGE (VCCO)
9 OUTPUT TRANSITION TIME (ns) 8 7 6 5 4 3 2 1 0 RNG1 = LOW 1.8 2.1 2.4 2.7 3.0 3.3 tF tR
MAX9248/50 toc03
70 60 SUPPLY CURRENT (mA) 50 40 30 20 10 0 0 5 10 15 20 25 30 35 40 MAX9250 MAX9248
6 OUTPUT TRANSITION TIME (ns) 5 4 3 2 1 RNG1 = HIGH 0 tR
10
tF
45
1.8
2.1
2.4
2.7
3.0
3.3
FREQUENCY (MHz)
OUTPUT SUPPLY VOLTAGE (V)
OUTPUT SUPPLY VOLTAGE (V)
OUTPUT POWER SPECTRUM vs. FREQUENCY (REFCLK = 42MHz, NO SPREAD, 4%, AND 2% SPREAD)
MAX9248/50 toc04
BIT-ERROR RATE vs. CABLE LENGTH
CAT5 CABLE
MAX9248/50 toc05
CABLE LENGTH vs. FREQUENCY BIT-ERROR RATE < 10-9
40 35 FREQUENCY (MHz) 30 25 20 15 10 5
MAX9248/50 toc06
0 -10 POWER SPECTRUM (dBm) -20 -30 -40 -50 -60 -70
1.00E-14
45
RESOLUTION BW = 30kHz VIDEO BW = 100kHz
NO SPREAD 2% SPREAD 4% SPREAD
1.00E-13 BIT-ERROR RATE
1.00E-12
39
40
41
42
43
44
45
1.00E-11 REFCLK = 42MHz 840Mbps DATA RATE FOR CABLE LENGTH < 10m BER < 10-12 1.00E-10 0 2 4 6
8
10
12
0
2
4
6
8
10 12 14 16 18 20
FREQUENCY (MHz)
CAT5 CABLE LENGTH (m)
CABLE LENGTH (m)
6
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27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers
Pin Description
PIN MAX9248 MAX9250 1 1 NAME FUNCTION Rising or Falling Latch Edge Select. LVTTL/LVCMOS input. Selects the edge of PCLK_OUT for latching data into the next chip. Set R/F = high for a rising latch edge. Set R/F = low for a falling latch edge. Internally pulled down to GND. LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel clock input frequency. Internally pulled down to GND. LVDS Supply Voltage. Bypass to LVDSGND with 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. Noninverting LVDS Serial-Data Input Inverting LVDS Serial-Data Input LVDS Supply Ground PLL Supply Ground PLL Supply Voltage. Bypass to PLLGND with 0.1F and 0.001F capacitors in parallel as close to the device as possible with the smallest value capacitor closest to the supply pin. LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel clock input frequency. Internal pulldown to GND. Digital Supply Ground Digital Supply Voltage. Supply for LVTTL/LVCMOS inputs and digital circuits. Bypass to GND with 0.1F and 0.001F capacitors in parallel as close to the device as possible with the smallest value capacitor closest to the supply pin. LVTTL/LVCMOS Reference Clock Input. Apply a reference clock that is within 2% of the serializer PCLK_IN frequency. Internally pulled down to GND. LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND. LVTTL/LVCMOS Spread-Spectrum Input. SS selects the frequency spread of PCLK_OUT and output data relative to PCLK_IN. Drive SS high for 4% spread and pull low for 2% spread.
MAX9248/MAX9250
R/F
2 3 4 5 6 7 8 9 10 11
2 3 4 5 6 7 8 9 10 11
RNG1 VCCLVDS IN+ INLVDSGND PLLGND VCCPLL RNG0 GND VCC
12 13 14
12 13 --
REFCLK PWRDWN SS
15-23
15-23
LVTTL/LVCMOS Control Data Outputs. CNTL_OUT[8:0] are latched into the next chip on the CNTL_OUT0- rising or falling edge of PCLK_OUT as selected by R/F when DE_OUT is low, and are held CNTL_OUT8 at the last state when DE_OUT is high. DE_OUT VCCOGND VCCO LVTTL/LVCMOS Data-Enable Output. High indicates RGB_OUT[17:0] are active. Low indicates CNTL_OUT[8:0] are active. Output Supply Ground Output Supply Voltage. Bypass to GND with 0.1F and 0.001F capacitors in parallel as close to the device as possible with the smallest value capacitor closest to the supply pin.
24 25, 37 26, 38
24 25, 37 26, 38
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7
27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers MAX9248/MAX9250
Pin Description (continued)
PIN MAX9248 MAX9250 27 28 29-36, 39-48 27 28 29-36, 39-48 NAME LOCK PCLK_OUT RGB_OUT0- RBG_OUT7, RGB_OUT8- RGB_OUT17 FUNCTION LVTTL/LVCMOS Lock Indicator Output. Outputs are valid when LOCK is low. LVTTL/LVCMOS Parallel Clock Output. Latches data into the next chip on the edge selected by R/F. LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Outputs. RGB_OUT[17:0] are latched into the next chip on the edge of PCLK_OUT selected by R/F when DE_OUT is high, and are held at the last state when DE_OUT is low. LVTTL/LVCMOS Output Enable Input. High activates the single-ended outputs. Driving low places the single-ended outputs in high impedance except LOCK. Internally pulled down to GND.
--
14
OUTEN
Functional Diagram
R/F DC BALANCE/ DECODE DC BALANCE/ DECODE SER-TO-PAR IN+ IN1 FIFO 0 SER-TO-PAR RGB_OUT CNTL_OUT DE_OUT PCLK_OUT PCLK_OUT REFCLK PLL SSPLL TIMING AND CONTROL SS PWRDWN LOCK TIMING AND CONTROL REFCLK PLL REF_IN PWRDWN LOCK IN+ IN1 0 R/F OUTEN RGB_OUT CNTL_OUT DE_OUT
MAX9248
RNG[0:1] RNG[0:1]
MAX9250
8
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27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers MAX9248/MAX9250
IN+ RIB 1.2V LVDS RECEIVER ODD RGB_OUT CNTL_OUT EVEN RGB_OUT CNTL_OUT RISING LATCH EDGE SHOWN (R/F = HIGH). PCLK_OUT
RIB IN-
Figure 1. LVDS Input Bias
Figure 2. Worst-Case Output Pattern
DE_OUT LOCK PCLK_OUT RGB_OUT[17:0] CNTL_OUT[8:0] tR
0.9 x VCCO
PCLK_OUT 2.0V tHIGH 0.8V
0.1 x VCCO tF tLOW
Figure 3. Output Rise and Fall Times
Figure 4. High and Low Times
PCLK_OUT 0.8V
2.0V
PCLK_OUT SHOWN FOR R/F = HIGH (RISING LATCH EDGE) tDVB DE_OUT LOCK RGB_OUT[17:0] CNTL_OUT[8:0] 2.0V 0.8V 2.0V 0.8V tDVA
Figure 5. Synchronous Output Timing
20 SERIAL BITS PCLK_OUT SHOWN FOR R/F = HIGH
IN+, IN-
SERIAL-WORD N
SERIAL-WORD N + 1 tDELAY
PCLK_OUT CNTL_OUT RGB_OUT PARALLEL-WORD N - 1 PARALLEL-WORD N
Figure 6. Deserializer Delay
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27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers MAX9248/MAX9250
2.0V PWRDWN 0.8V tPLLREF TRANSITION WORD FOUND tPDD
REFCLK
RECOVERED CLOCK PCLK_OUT HIGH IMPEDANCE HIGH IMPEDANCE
CLOCK STRETCH VALID DATA RGB_OUT CNTL_OUT DE_OUT HIGH IMPEDANCE HIGH IMPEDANCE
LOCK
HIGH IMPEDANCE
HIGH IMPEDANCE
NOTE: R/F = HIGH
Figure 7. PLL Lock to REFCLK and Power-Down Delay for MAX9250
2.0V PWRDWN 0.8V tPLLREF TRANSITION WORD FOUND 288 CLOCK CYCLES tPDD
REFCLK OUTPUT CLOCK SPREAD PCLK_OUT HIGH IMPEDANCE OUTPUT DATA SPREAD VALID DATA RGB_OUT CNTL_OUT DE_OUT HIGH IMPEDANCE HIGH IMPEDANCE HIGH IMPEDANCE
CLOCK STRETCH
LOCK
HIGH IMPEDANCE
HIGH IMPEDANCE
NOTE: R/F = HIGH
Figure 8. PLL Lock to REFCLK and Power-Down Delay for MAX9248
10
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27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers MAX9248/MAX9250
OUTEN 0.8V tOE DE_OUT RGB_OUT[17:0] CNTL_OUT[8:0] DE_OUT RGB_OUT[17:0] HIGH IMPEDANCE ACTIVE CNTL_OUT[8:0] ACTIVE HIGH IMPEDANCE OUTEN 2.0V
MAX9250
tOZ
MAX9250
Figure 9. Output Enable Time
Figure 10. Output Disable Time
FREQUENCY 1 / fSSM
fRxCLKOUT (MAX)
fRxCLKIN
TIME
fRxCLKOUT (MIN)
Figure 11. Simplified Modulation Profile
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11
27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers MAX9248/MAX9250
Detailed Description
The MAX9248/MAX9250 DC-balanced deserializers operate at a 2.5MHz-to-42MHz parallel clock frequency, deserializing video data to the RGB_OUT[17:0] outputs when the data-enable output DE_OUT is high, or control data to the CNTL_OUT[8:0] outputs when DE_OUT is low. The outputs on the MAX9248 are programmable for 2% or 4% spread relative to the LVDS input clock frequency, while the MAX9250 has no spread, but has an output-enable input that allows output busing. The video phase words are decoded using two overhead bits, EN0 and EN1. Control phase words are decoded with one overhead bit, EN0. Encoding, performed by the MAX9247 serializer, reduces EMI and maintains DC balance across the serial cable. The serial-input word formats are shown in Tables 1 and 2. Control data inputs C0 to C4, each repeated over three serial bit times by the serializer, are decoded using majority voting. Two or three bits at the same state determine the state of the recovered bit, providing single bit-error tolerance for C0 to C4. The state of C5 to C8 is determined by the level of the bit itself (no voting is used). The MAX9247 serializer can also be DC-coupled to the MAX9248/MAX9250 deserializers. Figures 12 and 14 show the AC-coupled serializer and deserializer with two capacitors per link, and Figures 13 and 15 show the AC-coupled serializer and deserializer with four capacitors per link.
Applications Information
Selection of AC-Coupling Capacitors
See Figure 16 for calculating the capacitor values for AC-coupling depending on the parallel clock frequency. The plot shows capacitor values for two- and fourcapacitor-per-link systems. For applications using less than 18MHz clock frequency, use 0.1F capacitors.
Termination and Input Bias
The IN+ and IN- LVDS inputs are internally connected to +1.2V through 42k (min) to provide biasing for ACcoupling (Figure 1). Assuming 100 interconnect, the LVDS input can be terminated with a 100 resistor. Match the termination to the differential impedance of the interconnect. Use a Thevenin termination, providing 1.2V bias, on an AC-coupled link in noisy environments. For interconnect with 100 differential impedance, pull each LVDS line up to VCC with 130 and down to ground with 82 at the deserializer input (Figures 12 and 15). This termination provides both differential and common-mode termination. The impedance of the Thevenin termination should be half the differential impedance of the interconnect and provide a bias voltage of 1.2V.
AC-Coupling Benefits
AC-coupling increases the input voltage of the LVDS receiver to the voltage rating of the capacitor. Two capacitors are sufficient for isolation, but four capacitors--two at the serializer output and two at the deserializer input--provide protection if either end of the cable is shorted to a high voltage. AC-coupling blocks low-frequency ground shifts and common-mode noise.
Table 1. Serial Video Phase Word Format
0 EN0 1 EN1 2 S0 3 S1 4 S2 5 S3 6 S4 7 S5 8 S6 9 S7 10 S8 11 S9 12 S10 13 S11 14 S12 15 S13 16 S14 17 S15 18 S16 19 S17
Bit 0 is the LSB and is deserialized first. EN[1:0] are encoding bits. S[17:0] are encoded symbols.
Table 2. Serial Control Phase Word Format
0 EN0 1 C0 2 C0 3 C0 4 C1 5 C1 6 C1 7 C2 8 C2 9 C2 10 C3 11 C3 12 C3 13 C4 14 C4 15 C4 16 C5 17 C6 18 C7 19 C8
Bit 0 is the LSB and is deserialized first. C[8:0] are the mapped control inputs.
12
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27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers MAX9248/MAX9250
VCC 130 * OUT * 82 82 IN 130 DC BALANCE/ DECODE SER-TO-PAR 1 0
PRE DC BALANCE/ ENCODE INPUT LATCH RGB_IN CNTL_IN DE_IN 1 0 PAR-TO-SER
R/F OUTEN RGB_OUT CNTL_OUT DE_OUT
CMF
RNG0 PCLK_IN RNG0 RNG1 PWRDWN PLL TIMING AND CONTROL RNG1
PCLK_OUT PLL REF_IN TIMING AND CONTROL PWRDWN LOCK
MAX9247
MAX9250
CERAMIC RF SURFACE-MOUNT CAPACITOR
100 DIFFERENTIAL STP CABLE
*CAPACITORS CAN BE AT EITHER END.
Figure 12. AC-Coupled MAX9247 Serializer and MAX9250 Deserializer with Two Capacitors per Link
VCC 130 130 DC BALANCE/ DECODE SER-TO-PAR 1 0
PRE DC BALANCE/ ENCODE INPUT LATCH RGB_IN CNTL_IN DE_IN 1 0 PAR-TO-SER
R/F OUTEN RGB_OUT CNTL_OUT DE_OUT
OUT 82 82
IN
CMF
RNG0 PCLK_IN RNG0 RNG1 PWRDWN PLL TIMING AND CONTROL RNG1
PCLK_OUT PLL REF_IN TIMING AND CONTROL PWRDWN LOCK
MAX9247
MAX9250
CERAMIC RF SURFACE-MOUNT CAPACITOR
100 DIFFERENTIAL STP CABLE
Figure 13. AC-Coupled MAX9247 Serializer and MAX9250 Deserializer with Four Capacitors per Link
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13
27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers MAX9248/MAX9250
VCC 130 * PAR-TO-SER OUT * 82 130 DC BALANCE/ DECODE SER-TO-PAR IN+ IN82 1 FIFO 0
PRE RGB_IN CNTL_IN DE_IN DC BALANCE/ ENCODE INPUT LATCH 1 0
R/F RGB_OUT CNTL_OUT DE_OUT PCLK_OUT
CMF
PCLK_IN RNG0 RNG1 PWRDWN
REFCLK PLL TIMING AND CONTROL
PLL SSPLL TIMING AND CONTROL SS PWRDWN LOCK
MAX9247
RNG[0:1] CERAMIC RF SURFACE-MOUNT CAPACITOR *CAPACITORS CAN BE AT EITHER END. 100 DIFFERENTIAL STP CABLE
MAX9248
Figure 14. AC-Coupled MAX9247 Serializer and MAX9248 Deserializer with Two Capacitors per Link
VCC 130 130 DC BALANCE/ DECODE SER-TO-PAR IN+ OUT IN82 82 1 FIFO 0
PRE DC BALANCE/ ENCODE INPUT LATCH RGB_IN CNTL_IN DE_IN PAR-TO-SER 1 0
R/F RGB_OUT CNTL_OUT DE_OUT PCLK_OUT
CMF
PCLK_IN RNG0 RNG1 PWRDWN
REFCLK PLL TIMING AND CONTROL
PLL SSPLL TIMING AND CONTROL SS PWRDWN LOCK
MAX9247
RNG[0:1] CERAMIC RF SURFACE-MOUNT CAPACITOR 100 DIFFERENTIAL STP CABLE
MAX9248
Figure 15. AC-Coupled MAX9247 Serializer and MAX9248 Deserializer with Four Capacitors per Link
14
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27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers
Input Frequency Detection
A frequency-detection circuit detects when the LVDS input is not switching. When not switching, all outputs except LOCK are low, LOCK is high, and PCLK_OUT follows REFCLK. This condition occurs, for example, if the serializer is not driving the interconnect or if the interconnect is open.
140 120 CAPACITOR VALUE (nF) 100 80 60 40 20 TWO CAPACITORS PER LINK 0 18 21 24 27 30 33 36 39 42 PARALLEL CLOCK FREQUENCY (MHz) FOUR CAPACITORS PER LINK
MAX9248/MAX9250
Frequency Range Setting (RNG[1:0])
The RNG[1:0] inputs select the operating frequency range of the MAX9248/MAX9250 and the transition time of the outputs. Select the frequency range that includes the MAX9247 serializer PCLK_IN frequency. Table 3 shows the selectable frequency ranges and the corresponding data rates and output transition times.
Table 3. Frequency Range Programming
RNG1 0 0 1 1 RNG0 0 1 0 1 PARALLEL CLOCK (MHz) 2.5 to 5.0 5 to 10 10 to 20 20 to 42 SERIALDATA RATE (Mbps) 50 to 100 100 to 200 200 to 400 400 to 840 OUTPUT TRANSITION TIME Slow Fast
Figure 16. AC-Coupling Capacitor Values vs. Clock Frequency of 18MHz to 42MHz
Power Down
Driving PWRDWN low puts the outputs in high impedance and stops the PLL. With PWRDWN 0.3V and all LVTTL/LVCMOS inputs 0.3V or VCC - 0.3V, the supply current is reduced to less than 50A. Driving PWRDWN high initiates lock to the local reference clock (REFCLK) and afterwards to the serial input.
Lock and Loss-of-Lock (LOCK)
When PWRDWN is driven high, the PLL begins locking to REFCLK, drives LOCK from high impedance to high and the other outputs from high impedance to low, except PCLK_OUT. PCLK_OUT outputs REFCLK while the PLL is locking to REFCLK. Lock to REFCLK takes a maximum of 16,928 REFCLK cycles for the MAX9250. The MAX9248 has an additional spread-spectrum PLL (SSPLL) that also begins locking to REFCLK. Locking both PLLs to REFCLK takes a maximum of 33,600 REFCLK cycles for the MAX9248.
When the MAX9248/MAX9250 complete their lock to REFCLK, the serial input is monitored for a transition word. When a transition word is found, LOCK output is driven low, indicating valid output data and the parallel rate clock recovered from the serial input is output on PCLK_OUT. The MAX9248 SSPLL waits an additional 288 clock cycles after the transition word is found before LOCK is driven low and sequence takes effect. PCLK_OUT is stretched on the change from REFCLK to recovered clock (or vice versa) at the time when the transition word is found. If a transition word is not detected within 222 cycles of PCLK_OUT, LOCK is driven high, the other outputs except PCLK_OUT are driven low. REFCLK is output on PCLK_OUT and the deserializer continues monitoring the serial input for a transition word. See Figure 7 for the MAX9250 and Figure 8 for the MAX9248 regarding the synchronization timing diagram. The MAX9248 input-to-output delay can be as low as (4.5t T + 8.0)ns or as high as (36t T + 16)ns due to spread-spectrum variations (see Figure 6). The MAX9250 input-to-output delay can be as low as (3.575tT + 8)ns or as high as (3.725tT + 16)ns.
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15
27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers MAX9248/MAX9250
Spread-Spectrum Selection
The MAX9248 single-ended data and clock outputs are programmable for a variation of 2% or 4% around the LVDS input clock frequency. The modulation rate of the frequency variation is 32kHz for a 33MHz LVDS clock input and scales linearly with the clock frequency (see Table 4). The output spread is controlled through the SS input (see Table 5). Driving SS high spreads all data and clock outputs by 4%, while pulling low spreads 2%. Any spread change causes a delay time of 32,000 x tT before output data is valid. When the spread amount is changed from 2% to 4% or vice versa, the data outputs go low for one tSSPLL delay (see Figure 17). The data outputs stay low, but are not valid when the spread amount is changed.
Output Enable (OUTEN) and Busing Outputs
The outputs of two MAX9250s can be bused to form a 2:1 mux with the outputs controlled by the output enable. Wait 30ns between disabling one deserializer (driving OUTEN low) and enabling the second one (driving OUTEN high) to avoid contention of the bused outputs. OUTEN controls all outputs except LOCK.
Table 4. Modulation Rate
fPCLK_IN 8 10 16 32 40 42 fM(kHz) = fPCLK_IN / 1024 7.81 9.77 15.63 31.25 39.06 41.01
Rising or Falling Output Latch Edge (R/F)
The MAX9248/MAX9250 have a selectable rising or falling output latch edge through a logic setting on R/F. Driving R/F high selects the rising output latch edge, which latches the parallel output data into the next chip on the rising edge of PCLK_OUT. Driving R/F low selects the falling output latch edge, which latches the parallel output data into the next chip on the falling edge of PCLK_OUT. The MAX9248/MAX9250 outputlatch-edge polarity does not need to match the MAX9247 serializer input-latch-edge polarity. Select the latch-edge polarity required by the chip being driven by the MAX9248/MAX9250.
Table 5. SS Function
SS INPUT LEVEL High Low OUTPUT SPREAD Data and clock output spread 4% relative to REFCLK Data and clock output spread 2% relative to REFCLK
SS
4% OR 2% SPREAD
4% OR 2% SPREAD
tSSPLL (32,800 x tT) PCLK_OUT
RGB_OUT[17:0] CNTL_OUT8:0]
LOW
LOCK
Figure 17. Output Waveforms when Spread Amount is Changed
16
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27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers MAX9248/MAX9250
CONTROL DATA VIDEO DATA CONTROL DATA
PCLK_OUT
CNTL_OUT
DE_OUT
RGB_OUT
PCLK_OUT TIMING SHOWN FOR R/F = HIGH (RISING OUTPUT LATCH EDGE) = OUTPUT DATA HELD
Figure 18. Output Timing
Staggered and Transition Time Adjusted Outputs
RGB_OUT[17:0] are grouped into three groups of six, with each group switching about 1ns apart in the video phase to reduce EMI and ground bounce. CNTL_OUT[8:0] switch during the control phase. Output transition times are slower in the 2.5MHz to 5MHz and 5MHz to 10MHz ranges and faster in the 10MHz to 20MHz and 20MHz to 42MHz ranges.
* * *
Power up the MAX9247 first Wait for at least tLOCK of MAX9247 (or 17100 x tT) to get activity on the link Power up the MAX9248
Power-Supply Circuits and Bypassing
There are separate on-chip power domains for digital circuits and LVTTL/LVCMOS inputs (VCC supply and GND), outputs (V CCO supply and V CCOGND ), PLL (V CCPLL supply and PLLGND), and the LVDS input (VCCLVDS supply and LVDSGND). The grounds are isolated by diode connections. Bypass each VCC, VCCO, VCCPLL, and VCCLVDS pin with high-frequency, surface-mount ceramic 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. The outputs are powered from V CCO , which accepts a 1.71V to 3.6V supply, allowing direct interface to inputs with 1.8V to 3.3V logic levels.
Data-Enable Output (DE_OUT)
The MAX9248/MAX9250 deserialize video and control data at different times. Control data is deserialized during the video blanking time. DE_OUT high indicates that video data is being deserialized and output on RGB_OUT[17:0]. DE_OUT low indicates that control data is being deserialized and output on CNTL_OUT[8:0]. When outputs are not being updated, the last data received is latched on the outputs. Figure 18 shows the DE_OUT timing.
Power-Supply Sequencing of MAX9247 and MAX9248/MAX9250 Video Link
The MAX9247 and MAX9248/MAX9250 video link can be powered up in several ways. The best approach is to keep both MAX9247 and MAX9248 powered down while supplies are ramping up and PCLK_IN of the MAX9247 and REFCLK of the MAX9248/MAX9250 are stabilizing. After all of the power supplies of the MAX9247 and MAX9248/MAX9250 are stable, including PCLK_IN and REFCLK, do the following:
Cables and Connectors
Interconnect for LVDS typically has a differential impedance of 100. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver.
17
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27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers MAX9248/MAX9250
1M CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 100pF RD 1.5k DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST HIGHVOLTAGE DC SOURCE CHARGE-CURRENTLIMIT RESISTOR CS 150pF R2 330 DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST
Figure 19. Human Body ESD Test Circuit
Figure 20. IEC 61000-4-2 Contact Discharge ESD Test Circuit
RD 2k CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 330pF DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST HIGHVOLTAGE DC SOURCE CHARGE-CURRENTLIMIT RESISTOR CS 200pF
RD 0 DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST
Figure 21. ISO 10605 Contact Discharge ESD Test Circuit
Figure 22. Machine Model ESD Test Circuit
Board Layout
RGB_OUT17 RGB_OUT16 RGB_OUT15
RGB_OUT14 RGB_OUT13 RGB_OUT12 RGB_OUT11
ESD Protection
The MAX9248/MAX9250 ESD tolerance is rated for Human Body Model, Machine Model, IEC 61000-4-2 and ISO 10605. The ISO 10605 and IEC 61000-4-2 standards specify ESD tolerance for electronic systems. All LVDS inputs on the MAX9248/MAX9250 meet ISO 10605 ESD protection at 30kV Air-Gap Discharge and 10kV Contact Discharge and IEC 61000-4-2 ESD protection at 15kV Air-Gap Discharge and 10kV Contact Discharge. All other pins meet the Human Body Model ESD tolerance of 2kV. The Human Body Model discharge components are CS = 100pF and RD = 1.5k (Figure 19). The IEC 61000-4-2 discharge components are CS = 150pF and RD = 330 (see Figure 20). The ISO 10605 discharge components are CS = 330pF and RD = 2k (Figure 21). The Machine Model discharge components are CS = 200pF and RD = 0 (Figure 22).
R/F RNG1 VCCLVDS IN+ INLVDSGND PLLGND VCCPLL RNG0 GND VCC REFCLK
1 2 3 4 5 6 7 8 9 10 11 12
48
47
46
45
44
43
42
41
40
39
38
37
VCCOGND
TOP VIEW
RGB_OUT10 RGB_OUT9 RGB_OUT8 VCCO
Separate the LVTTL/LVCMOS outputs and LVDS inputs to prevent crosstalk. A four-layer PCB with separate layers for power, ground, and signals is recommended.
Pin Configuration
36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24
RGB_OUT7 RGB_OUT6 RGB_OUT5 RGB_OUT4 RGB_OUT3 RGB_OUT2 RGB_OUT1 RGB_OUT0 PCLK_OUT LOCK VCCO VCCOGND
MAX9248/MAX9250
PWRDWN SS (OUTEN)
CNTL_OUT0 CNTL_OUT1 CNTL_OUT2 CNTL_OUT3 CNTL_OUT4
CNTL_OUT5 CNTL_OUT6 CNTL_OUT7 CNTL_OUT8
LQFP
18
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DE_OUT
27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers
Chip Information
PROCESS: CMOS
PACKAGE TYPE 48 LQFP
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE CODE C48+3 DOCUMENT NO. 21-0054
MAX9248/MAX9250
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19
27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers MAX9248/MAX9250
Revision History
REVISION NUMBER 2 3 REVISION DATE 5/08 4/09 DESCRIPTION Replaced TQFP and TQFN packages with LQFP package, changed temperature limits for +105C part, and added Machines Model ESD text and diagram Added /V parts in the Ordering Information table and added new PowerSupply Sequencing of MAX9247 and MAX9248/MAX9250 Video Link section PAGES CHANGED 1-5, 7, 16-19 1, 17
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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